Overview of the Company We are one of the leading independent providers of semiconductor assembly and testing services. Specifically, we are one of the leading independent providers of testing and assembly services for LCD, OLED, automotive panel and other display panel driver semiconductors and advanced memory and logic/mixed-signal products in Taiwan. The depth of our engineering expertise and the breadth of our assembly and testing technologies enable us to provide our customers with advanced and comprehensive assembly and testing services. In addition, our geographic presence in Taiwan is attractive to customers wishing to take advantage of the logistical and cost efficiencies stemming from our close proximity to foundries and producers of consumer electronic products in Taiwan. Our production facilities are located in Hsinchu and Tainan, Taiwan. Our Structure and History We are a company limited by shares, incorporated on July 28, 1997, under the ROC Company Act, under the name “ChipMOS TECHNOLOGIES INC.” (“ChipMOS Taiwan”), as a joint venture company between Mosel Vitelic Inc. (“Mosel”) and Siliconware Precision Industries Co., Ltd. (“Siliconware Precision”) and with the participation of other investors. Our operations consist of the assembly and testing of semiconductors as well as gold bumping and memory module manufacturing. Our principal place of business is located at No. 1, R&D Road 1, Hsinchu Science Park, Hsinchu, Taiwan, ROC and its phone number is +886-3-577-0055 and our internet website address is “www.chipmos.com”. The Company listed and commenced trading on the main board of TWSE on April 11, 2014. According to the merger agreement, entered between the Company and ChipMOS TECHNOLOGIES (Bermuda) LTD. (“ChipMOS Bermuda”) dated January 21, 2016 (the “Merger Agreement”), ChipMOS Bermuda merged with and into the Company, with the Company being the surviving company after the Merger. The transaction was accounted as capital reorganization within the Company and its subsidiaries (the “Group”), please see “Item 5. Operating and Financial Review and Prospects—Recent Acquisitions”. Any common shares of ChipMOS Bermuda issued and outstanding immediately prior to the effective time of the Merger was cancelled and, in exchange, each former holder of such cancelled common shares of ChipMOS Bermuda was entitled to receive, with respect to each such share (i) US$3.71 in cash, without interest, and (ii) 0.9355 ADSs representing 18.71 shares of the Company (each ADS representing 20 new common shares, par value of NT$10 each, to be issued by the Company) in exchange for each of ChipMOS Bermuda’s common share held (the US$3.71 in cash and together with the ADSs, the “Merger Consideration”). The Merger was completed and effective on October 31, 2016. The Company issued 512,405,340 common shares represented by the ADSs and the ADSs were listed on the Nasdaq on November 1, 2016. 16 The following chart illustrates our corporate structure and our equity interest in each of our principal subsidiaries as of the date of this Annual Report on Form 20-F. Note: (1)Under IFRS 10, “Consolidated Financial Statements”, we are required to consolidate the financial results of any subsidiaries in which we hold a controlling interest or voting interest in excess of 50% or we have the power to direct or cause the direction of the management and policies, notwithstanding the lack of majority ownership. Since 2020, we have consolidated the financial results of ChipMOS U.S.A., Inc. (“ChipMOS USA”), ChipMOS BVI, and ChipMOS SEMICONDUCTORS (Shanghai) LTD. (“ChipMOS Shanghai”), a wholly-owned subsidiary of ChipMOS BVI. Agreements with Tsinghua Unigroup Ltd. On November 30, 2016, the Equity Interest Transfer Agreements among ChipMOS BVI, a wholly-owned subsidiary of the Company, and some strategic investors which including Unigroup Guowei, a subsidiary of Tsinghua Unigroup, were executed. Pursuant to the Equity Interest Transfer Agreements, ChipMOS BVI would sell 54.98% equity interests of its wholly-owned subsidiary, Unimos Shanghai, to the strategic investors, and Unigroup Guowei would hold 48% equity interests of Unimos Shanghai, and the other strategic investors, including a limited partnership owned by Unimos Shanghai’s employees, would own approximately 6.98% equity interest of Unimos Shanghai. The transaction was completed in March 2017. Unimos Shanghai is no longer the subsidiary of the Company following the completion of equity interest transfer. Also pursuant to the agreement, ChipMOS BVI and the strategic investors agreed to further invest RMB 1,074 million into Unimos Shanghai. The further investment was completed in two tranches, one in July 2017 at RMB 687 million and one in February 2018 at RMB 387 million. On December 16, 2019, Unigroup Guowei and one of the strategic investor sold and transferred all equity interests of Unimos Shanghai to Yangtze Memory, which holds 50% equity interests of Unimos Shanghai after completed transaction. On May 11, 2020, one of the strategic investor sold and transferred all equity interests of Unimos Shanghai to Yangtze Memory Technologies Co., Ltd. (“Yangtze Memory”), which holds 50.94% equity interests of Unimos Shanghai after completed transaction. On July 24, 2023, Yangtze Memory sold and transferred all equity interests of Unimos Shanghai to Yangtze Memory Technologies Holding Co., Ltd., (“Yangtze Memory Holding”), which holds 50.94% equity interests of Unimos Shanghai after completed transaction. 17 Agreements with Suzhou Oriza PuHua ZhiXin Equity Investment Partnership (L.P.) On December 21, 2023, the Company’s Board of Directors approved its wholly-owned subsidiary, ChipMOS BVI to sell its entire 45.0242% equity interests in Unimos Shanghai for a total sale price of RMB 979.3 million in cash. Under the agreement, ChipMOS BVI sold its entire remaining 45.0242% equity interests in Unimos Shanghai to Suzhou Oriza PuHua ZhiXin Equity Investment Partnership (L.P.) and other local Chinese investment management companies. ChipMOS BVI completed the equity interest transfer of Unimos Shanghai in May 2024, and fully received the consideration amounted in December 2024. For additional information on the transaction, see “Item 5. Operating and Financial Review and Prospects—Recent Acquisition”. Our Principal Consolidated Subsidiaries Below is a description of our principal consolidated subsidiaries: ChipMOS TECHNOLOGIES (BVI) LTD., or formerly known as MODERN MIND TECHNOLOGY LIMITED ChipMOS BVI was incorporated in the British Virgin Islands in January 2002. ChipMOS SEMICONDUCTORS (Shanghai) LTD. ChipMOS Shanghai was incorporated in Mainland China in March 2020, which is a wholly-owned subsidiary of ChipMOS BVI. It primarily engaged in providing marketing of semiconductors and electronic related produces, for its parent company and affiliates, throughout Mainland China. ChipMOS U.S.A., Inc. ChipMOS USA was incorporated in the United States of America in October 1999. It is primarily engaged in providing marketing of semiconductors and electronic related produces, for its parent company and affiliates, throughout the United States of America. ChipMOS USA began generating revenue in 2001. Industry Background We provide a broad range of back-end assembly and testing services. Testing services include engineering test, wafer probing and final test of memory and logic/mixed-signal semiconductors. We also offer a broad selection of leadframe- and organic substrate-based package assembly services for memory and logic/mixed-signal semiconductors. In addition, we provide gold bumping, reel to reel assembly and testing services for LCD, OLED, automotive panel and other display panel driver semiconductors by employing COF and COG technologies. Semiconductors tested and assembled by us are used in personal computers, graphics applications such as game consoles, communications equipment, mobile products, such as cellular handsets, tablets, consumer electronic products, automotive/industry and display applications such as display panels. In 2025, 23.7% of our revenue was derived from testing services for memory and logic/mixed-signal semiconductors, 28.6% from assembly services for memory and logic/mixed-signal semiconductors, 24.5% from Display panel driver semiconductor assembly and testing services and 23.2% from bumping services for semiconductors, respectively. In additional, stable long-term demand and high margin are basic characters of automotive application. More semiconductor chips and display panel are consumed with the trend of popularization of automotive panels and Electric Vehicle (EV) could benefit our margin and increase our earnings. Semiconductor Industry Trends Growth in the semiconductor industry is largely driven by end-user demand for consumer electronics, communications equipment and computers. Semiconductors are critical components of these products and applications. Geopolitics and tariff pressures are contributing factors to overall semiconductor industry supply chain inventory level increases and decreases in end-user demand, except AI. Ongoing fluctuations in our markets related to these factors potentially affect our results of operations. 18 Memory Semiconductor Market The potential for memory market growth is linked to anticipated memory content increases in consumer electronics, data center, wireless base-station, PC and smartphone applications due to updated system requirements (such as 5G & wifi 6), increasing use of storage, graphics in gaming and other applications. The memory market is dominated by two segments-DRAM and flash memory. Potential growth in the DRAM and NAND Flash market is expected to be driven by continued growth in both the commodity and niche DRAM market, as well as growth opportunities in mobile DRAM as memory requirements significantly increase for mobile applications and storage requirement for data center application. Flash memory market potential growth is expected to be driven by increasing memory requirements for cellular handsets, digital cameras, digital audio/video, server, wireless base-station and other mobile applications, and new application demand of NOR flash for automotive/industry, OLED panel and touch with display driver integration (TDDI). However, driven by improving demand for high-value memory solutions, particularly in data center and AI-related applications and EOL of DDR4 led memory in super cycle since second half of 2025. LCD, OLED, automotive panel and Other Display panel Driver Semiconductor Market Display panels are used in applications such as desktop monitors, notebooks, tables, television sets, cellular handsets and digital cameras. The end-user demand for LCD, OLED, automotive panel and other display panel driver semiconductors tends to very over time. The soft demand of TVs impacted our utilization level of COF assembly. Also, as more and more displays are installed in cars and EV, more driver IC grew for automotive application in 2025. Logic/Mixed-Signal Semiconductor Market The communications market is one of the main drivers of potential growth in the semiconductor industry. Logic/mixed-signal semiconductors, which are chips with analog functionality covering more than half of the chip area, are largely used in the communications market. The increasing use of digital technology in communications equipment requires chips with both digital and analog functionality for applications such as modems, network routers, switches, cable set-top boxes and cellular handsets. As the size and cost of cellular handsets and other communications-related devices have decreased, components have increased in complexity. Logic/mixed-signal semiconductors, such as LCD controller, power devices, fingerprint sensors and MEMS products, TV scaler and DVD controllers, are also used in consumer electronic products. We plan to expand our logic and mixed-signal product portfolio from MEMS and TV SOC products to include PMIC of DDR5 modules, logic product for smart devices serving high-tech and healthcare. We also plan to support ASIC for AI related application products to enhance the long-term growth momentum of our logic and mixed-signal product line. This represents a significant new market expansion opportunity. We view these as high return, multi-year opportunities with the potential to meaningfully drive growth and create shareholder value. Overview of the Semiconductor Manufacturing Process The manufacturing of semiconductors is a complex process that requires increasingly sophisticated engineering and manufacturing expertise. The manufacturing process may be broadly divided into the following stages: 19 Process Description Circuit Design The design of a semiconductor is developed by laying out circuit patterns and interconnections. Wafer Fabrication Wafer fabrication begins with the generation of a photomask, a photographic negative onto which a circuit design pattern is etched or transferred by an electron beam or laser beam writer. Each completed wafer contains many fabricated chips, each known as a die. Wafer Probe Each individual die is then electrically tested, or probed, for defects. Dies that fail this test are discarded, or, in some cases, salvaged using laser repair. Assembly The assembly of semiconductors serves to protect the die, facilitates its integration into electronic systems and enables the dissipation of heat. The process begins with the dicing of the wafers into chips. Each die is affixed to a leadframe-based or organic substrate-based substrate. Then, electrical connections are formed, in many cases by connecting the terminals on the die to the inner leads of the package using fine metal wires. Finally, each chip is encapsulated for protection, usually in a molded epoxy enclosure. Final Test Assembled semiconductors are tested to ensure that the device meets performance specifications. Testing takes place on specialized equipment using software customized for each application. For memory semiconductors, this process also includes “burn-in” testing to screen out defective devices by applying very high temperatures and voltages onto the memory device. Outsourcing Trends in Semiconductor Manufacturing Historically, integrated device manufacturers (“IDMs”), designed, manufactured, tested and assembled semiconductors primarily at their own facilities. In recent years, there has been a trend in the industry to outsource various segments of stages in the manufacturing process to reduce the high fixed costs resulting from the continuously more complex manufacturing process. Virtually every significant stage of the manufacturing process can be outsourced. The independent semiconductor manufacturing services market currently consists of wafer fabrication and probing services and semiconductor assembly and testing services. Most of the world’s major IDMs now use some independent semiconductor manufacturing services to maintain a strategic mix of internal and external manufacturing capacity. Many of these IDMs are continuously significantly reducing their investments in new semiconductor assembly and testing facilities. The availability of technologically advanced independent semiconductor manufacturing services has also enabled the growth of “fabless” semiconductor companies that focus exclusively on semiconductor design and marketing and outsource fabrication, assembly and testing requirements to independent companies. We believe the outsourcing of semiconductor manufacturing services, and in particular of assembly and testing services, will increase for many reasons, including the following: Significant Capital Expenditure Requirements. Driven by increasingly sophisticated technological requirements, wafer fabrication, assembly and testing processes have become highly complex, requiring substantial investment in specialized equipment and facilities and sophisticated engineering and manufacturing expertise. In addition, product life cycles have been shortened magnifying the need to continuously upgrade or replace manufacturing, assembly and testing equipment to accommodate new products. As a result, new investments in in-house fabrication, assembly and testing facilities are becoming less desirable for IDMs because of the high investment costs, as well as difficulties in achieving sufficient economies of scale and utilization rates to be competitive with the independent service providers. On the contrary, independent foundry, assembly and testing companies are able to realize the benefits of specialization and achieve economies of scale by providing services to a large customer base across a wide range of products. This enables them to reduce costs and shorten production cycles through high capacity utilization and process expertise. Increasing Focus on Core Competencies. As the costs of semiconductor manufacturing facilities increase, semiconductor companies are expected to further outsource wafer fabrication, assembly and testing requirements to focus their resources on core competencies, such as semiconductor design and marketing. Time-to-Market Pressure. Increasingly short product life cycles have amplified time-to-market pressure for semiconductor companies, leading them to rely more and more on independent companies as a key source for effective wafer fabrication, assembly and testing services. 20 Semiconductor Assembly and Testing Services Industry Growth in the semiconductor assembly and testing services industry is driven by increased outsourcing of the various stages of the semiconductor manufacturing process by IDMs and fabless semiconductor companies. The Semiconductor Industry and Conditions of Outsourcing in Taiwan and Mainland China Taiwan is one of the world’s leading locations for outsourced semiconductor manufacturing. The semiconductor industry supply chain in Taiwan has developed such that the various stages of the semiconductor manufacturing process have been disaggregated, thus allowing for specialization. The disaggregation of the semiconductor manufacturing process in Taiwan permits these semiconductor manufacturing service providers to focus on particular parts of the production process, develop economies of scale, maintain higher capacity utilization rates and remain flexible in responding to customer needs by lowering time-to-market pressure faced by semiconductor companies. There are several leading service providers in Taiwan, each of which offers substantial capacity, high-quality manufacturing, leading semiconductor wafer fabrication, test, assembly and process technologies, and a full range of services. These service providers have access to an educated labor pool and a large number of engineers suitable for sophisticated manufacturing industries. As a result, many of the world’s leading semiconductor companies outsource some or all of their semiconductor manufacturing needs to Taiwan’s semiconductor manufacturing service providers and take advantage of the close proximity among facilities in the supply chain. In addition, companies located in Taiwan are very active in the design and manufacture of electronic systems, which has created significant local demand for semiconductor devices. A few years ago, Mainland China had emerged as an attractive location for outsourced semiconductor manufacturing. Companies could take advantage of strongly supports by Mainland China government to accelerate the development of the semiconductor industry and a large domestic market. These factors had driven increased relocation of much of the electronics industry manufacturing and supply chain to Mainland China. But according to the economics uncertainty caused by the trade tensions and US semiconductor restrictions, the related investment risk in China is increasing. An increasing number of global electronic systems manufacturers and contract manufacturers are relocating or have relocated production facilities away from Mainland China. However, following the supply chain reshuffle after COVID-19, along with government subsidies and local production requirements, the competition pressure from DDIC supplier in Mainland China has gradually increased. Our Strategy Our goal is to reinforce our position as a leading independent provider of semiconductor assembly and testing services, concentrating principally on memory, logic/mixed-signal and OLED, automotive panel and other display panel driver semiconductors. The principal components of our business strategy are set forth below. Focus on Providing Our Services to Potential Growth Segments of the Semiconductor Industry. We intend to continue our focus on developing and providing advanced assembly and testing services for potential growth segments of the semiconductor industry, such as memory, logic/mixed-signal, OLED, automotive panel and other display panel driver semiconductors and bumping services. We believe that our investments in equipment and research and development in some of these areas allow us to offer a service differentiated from that of our competition. In order to benefit from the expected resumption of growth in these segments, we intend to continue to invest in capacity to meet the assembly and testing requirements of these key semiconductor market segments. Continue to Invest in the Research and Development of Advanced Assembly and Testing Technologies. Critical to our business growth is the continuation to expand our capabilities in testing and assembly and integrate wafer bumping and assembly core technologies to provide turn-key total solution service to our customers. We typically focus on advanced technologies that consist of greater potentials to generate higher margins. For example, we conducted new product introductions and on an on-going basis continue to expand our capabilities in fine-pitch wafer bumping, multi-chip package (“MCP”) and flip chip packaging. We are also introducing a low cost silver alloy bump products based on our intellectual property to service display panel market. We continue to maintain close working relationships with local and overseas research institutions and universities to keep abreast with leading edge technologies and broaden the scope of applications. In 2026, we focus our research and development efforts in the following areas: •Develop Eco-friendly with low curing-temperature PI materials for RDL redistribution products. •Develop a fluxless reflow process for Cu pillar products. •Development of ultra-fine pitch (IL pitch : 14 um) COF inner-lead flip-chip packaging technology. •Development of enhancement the 3PB face-down die strength packaging technology for LASER product. 21 •Develop multi-chip flash memory stacked BGA packaging technology. •Develop next-generation game card memory packaging technology. In 2025, we spent approximately 4.5% of our revenue on research and development. We will continue to invest our resources to recruit and retain experienced research and development personnel. As of February 28, 2026, our research and development team comprised 651 employees. Build on Our Strong Presence in Taiwan and Strong Industrial Position Outside Taiwan. We intend to build on our strong presence in key centers of semiconductor and electronics manufacturing to grow our business. Currently, most of our operations are in Taiwan, one of the world’s leading locations for outsourced semiconductor manufacturing. This presence provides us with several advantages. Firstly, our proximity to other semiconductor companies is attractive to customers who wish to outsource various stages of the semiconductor manufacturing process. Secondly, our proximity to many of our suppliers, customers and the end-users of our customers’ products enables us to be involved in the early stages of the semiconductor design process, enhances our ability to quickly respond to our customers’ changing requirements and shortens our customers’ time-to-market. Thirdly, we have access to an educated labor pool and a large number of engineers who are able to work closely with our customers and other providers of semiconductor manufacturing services. Depending on customer’s demands, market conditions and other relevant considerations, we may from time to time look into other opportunities to expand our operations outside of Taiwan. Expand Our Offering of Vertically Integrated Services. We believe that one of our competitive strengths is our ability to provide vertically integrated services to our customers. Vertically integrated services consist of the integrated testing, assembly and direct shipment of semiconductors to end-users designated by our customers. Providing vertically integrated services enables us to shorten lead times for our customers. Time-to-market and cost are sources of competitive advantage for our customers. As a result, our customers increasingly value our ability to provide them with comprehensive back-end services. We are able to offer vertically integrated services for a broad range of products, including memory, logic/mixed-signal and LCD, OLED, automotive panel and other display panel driver semiconductors. These services offerings include complementary technologies, products and services as well as additional capacity. We believe that these will continue to enhance our own development and expansion efforts into new and potential growth markets. We intend to establish new alliances with leading companies and, if suitable opportunities arise, engage in merger and acquisition activities that will further expand the services we can provide. Focus on Increasing Sales through Long-Term Agreements with Key Customers as well as Business with Smaller Customers. From time to time, we strategically agree to commit a portion of our assembly and testing capacity to certain of our customers. We intend to continue focus on increasing sales to key customers through long-term capacity agreements. The customers with which we entered long-term agreements include a reputable memory customer based in the U.S. See “—Customers” below for a more detailed discussion of these long-term agreements. Global market and economic conditions have been unprecedented and challenging with tight credit conditions and recession in most major economies since 2008. In the fourth quarter of 2021, a long term 3-year capacity secure agreement with our customer about high end wafer test for OLED and other display panel driver demand was settled to reduce our investment risk. Meanwhile, driven by the strong rebound in memory market since the second half of 2025, we finalized a long term 3-year memory wafer test capacity take-or-pay contract in the beginning of 2026. We also resumed our focus on our business with smaller customers or customers who do not place orders on a regular basis. We believe that the dual focused strategy will assist us to be better prepared for the current economic volatility and ensure maximum utilization rate of our capacity and help us to develop closer relationships with all types of our customers. 22 Principal Products and Services The following table presents, for the periods shown, revenue by service segment as a percentage of our revenue. Year ended December 31, 2023 2024 2025 Testing 20.6% 21.9% 23.7% Assembly 21.7% 23.8% 28.6% Display panel driver semiconductor assembly and testing 36.6% 32.2% 24.5% Bumping 21.1% 22.1% 23.2% Total revenue 100.0% 100.0% 100.0% Memory and Logic/Mixed-Signal Semiconductors Testing We provide testing services for memory and logic/mixed-signal semiconductors: Memory. We provide testing services for huge amount of varieties of memory semiconductors, such as SRAM, DRAM and Flash memory. To speed up the time-consuming process of memory product testing, we provide parallel test, which includes the completion of a tested wafer in one touchdown (up to 3,000 plus DUTs testing simultaneously). Wafer type includes Aluminum PAD, RDL PAD, Cu Pillar, WLCSP and prober test temperature between -55°~150° and provide 143MHz to 600 MHz test speed for DRAM product, 50MHz ~ 400 MHz test speed for FLASH product. Component type (FT) includes TSOP, BGA, LGA, WSON, SOP packages, the maximum parallel test is 512Dut per handler with a handler test temperature range between -55°~125° and support for test speed from 70MHz to 400 MHz for FLASH products, and 250MHz to 4.5GHz for DRAM products. The memory semiconductors we tested were applying primarily in desktop computers, laptop, tablet computers, handheld consumer electronic, devices and wireless communication devices. Logic/Mixed-Signal. We conduct tests on a wide variety of logic/mixed-signal semiconductors, with lead counts ranging from the single digits to over 1536 and data rate of up to 16Gbps. The semiconductors we test include high-end audio/video codec, networking/communications, MCU, LCD related, MEMS related, DDR related and automotive electronics used for home entertainment/media center, wearable devices, personal computer applications, network/communication, mobile smart devices and cars. We also test a variety of application specific integrated circuits (“ASICs”), for applications such as FHD/UHD/8K LCD TVs with AI functions, Smartphone, Tablet PC and Cars and other applications/end markets. The following is a description of our pre-assembly testing services: Wafer Probing. Wafer probing is a processing stage proceeding to the assembly of semiconductors and which involves visual inspection and electrical testing to ensure the processed wafers meets our customers’ specifications. Tests are conducted using specialized equipment with software customized for each application in different temperature conditions ranging from -55 degrees Celsius to 150 degrees Celsius. Wafer probing employs sophisticated design and manufacturing technologies to connect the terminals of each chip for testing. Defect chips are marked on the surface or memorized in an electronic file, known as a mapping file, to the following facilitate subsequent process. Laser Repairing. This is a unique process in testing operation for special SOC memory products. In laser repairing, specific poly or metal fuses are blown after wafer probing to enable a spare row or column of a memory unit in SOC the replacement of the defective memory cell. After assembly, we perform the following testing services: Burn-In Testing. This process screens out unreliable products using high temperature, high voltage and prolonged stresses environment to ensure that finished products will survive a long period of end-user service. This process is used only for memory products. This process needs customized Burn-In board. Top Marking. By using laser marker, the marking content were according to our customers’ specification, including the logo, part number, date code and lot number. Final Testing. Assembled semiconductors are tested to ensure that the devices meet performance specifications. Tests are conducted using specialized equipment with software customized for each application in different temperature conditions ranging from -55 degrees Celsius to 125 degrees Celsius. 23 Final Inspection and Packing. Final inspection involves visual or auto-inspection of the devices to check any bent leads, ball damage, inaccurate markings or other package defects. Packing involves dry packing, package-in-tray, package-in-tube and tape and reel. According to package level, Dry packing involves heating semiconductors in a tray at 125 degrees Celsius for about four to six hours to remove the moisture before the semiconductors are vacuum-sealed in an aluminum bag. Package-in-tube involves packing the semiconductors in anti-static tubes for shipment. Tape and reel pack involves transferring semiconductors from a tray or tube onto an anti-static embossed tape and rolling the tape onto a reel for shipment to customers. Assembly Our assembly services generally involve the following steps: Wafer Lapping The wafers are ground to their required thickness. Die Saw Wafers are cut into individual dies, or chips, in preparation for the die-attach process. Die Attach Each individual die is attached on the leadframe or organic substrate. Wire Bonding Using gold or silver wires, to connect the I/O pads on the die to the inner lead of leadframe or substrate. Flip Chip Bonding Using solder bumps or Cu pillar bumps on die, to connect the leadframe or substrate pad via soldering reflow. Molding The die and wires are encapsulated to provide physical support and protection. Marking Each individual package is marked to provide product identification. Dejunking and Trimming Mold flash is removed from between the lead shoulders through dejunking, and the dambar is cut during the trimming process. Electrical Plating A solderable coating is added to the package leads to prevent oxidization and to keep solder wettability of the package leads. Ball Mount and Reflow Each electrode pad of the substrate is first printed with flux, after which solder balls are mounted, heated and attached to the electrode pad of the substrate through a reflow oven. Forming/Singulation Forming involves the proper configuration of the device packages leads, and singulation separates the packages from each other. We offer a broad range of package formats designed to provide our customers with a broad array of assembly services. The assembly services we offer customers are leadframe-based packages, which include thin small outline packages, and organic substrate-based packages, including fine-pitch BGA. The differentiating characteristics of these packages include: •the size of the package; •the number of electrical connections which the package can support; •the electrical performance and requirements of the package; and •the heat dissipation requirements of the package. As new applications for semiconductor devices require smaller components, the size of packages has also decreased. In leading-edge packages, the size of the package is reduced to just slightly larger than the size of the individual chip itself in a process known as chip scale packaging. As semiconductor devices increase in complexity, the number of electrical connections required also increases. Leadframe-based products have electrical connections from the semiconductor device to the electronic product through leads on the perimeter of the package. Organic substrate-based products have solder balls on the bottom of the package, which create the electrical connections with the product and can support large numbers of electrical connections. Leadframe-Based Packages. These are generally considered the most widely used package category. Each package consists of a semiconductor chip encapsulated in a plastic molding compound with metal leads on the perimeter. This design has evolved from a design plugging the leads into holes on the circuit board to a design soldering the leads to the surface of the circuit board. 24 The following diagram presents the basic components of a standard leadframe-based package for memory semiconductors: To address the market for miniaturization of portable electronic products, we are currently developing and will continue to develop increasingly smaller versions of leadframe-based packages to keep pace with continually shrinking semiconductor device sizes. Our advanced leadframe-based packages generally are thinner and smaller, have more leads and have advanced thermal and electrical characteristics when compared to traditional packages. As a result of our continual product development, we offer leadframe-based packages with a wide range of lead counts and sizes to satisfy our customers’ requirements. The following table presents our principal leadframe-based packages, including the number of leads in each package, commonly known as lead-count, a description of each package and the end-user applications of each package. Package Lead- count Description End-User Applications Thin Small Outline Package I (TSOP I) 48-56 Designed for high volume production of low lead-count memory devices, including flash memory, SRAM and MROM Notebooks, personal computers, still and video cameras and standard connections for peripherals for computers Thin Small Outline Package II (TSOP II) 44-86 Designed for memory devices, including flash memory, SRAM, SDRAM and DDR DRAM Disk drives, recordable optical disk drives, audio and video products, consumer electronics, communication products Quad Flat No Lead (QFN) 8-132 Thermal enhanced quad flat no lead package providing small footprint (chip scale), light weight with good thermal and electrical performance Wireless communication products, notebooks, audio and video products and consumer electronics Low-Profile Quad Flat Package (LQFP) 48 Low-profile and light weight package designed for ASICs, digital signal processors, microprocessors/ controllers, graphics processors, gate arrays, SSRAM, SDRAM, personal computer chipsets and mixed-signal devices Wireless communication products, notebooks, digital cameras, cordless/radio frequency devices Small Outline Package (SOP) 8 Designed for low lead-count memory and logic semiconductors, including SRAM and micro-controller units Personal computers, consumer electronics, audio and video products, communication products Multi-Chip Package (TSOP) 44-86 Our patented design for memory devices, including flash memory, SRAM, DRAM, SDRAM and DDR DRAM Notebooks, personal computers, disk drives, audio and video products, consumer products, communication products 25 Package Lead- count Description End-User Applications Flip Chip Quad Flat No Lead (FCQFN) 6-35 Thermal enhanced quad flat no lead package providing small footprint (chip scale), light weight with good thermal and electrical performance Flip chip process is designed for better electrical performance compared to wire bonding process Wireless communication products, notebooks, audio/video products and consumer electronics Organic Substrate-based Packages. As the number of leads surrounding a traditional leadframe-based package increases, the leads must be placed closer together to reduce the size of the package. The close proximity of one lead to another can create electrical shorting problems and requires the development of continuously more sophisticated and expensive techniques to accommodate the high number of leads on the circuit boards. The BGA format solves this problem by effectively creating external terminals on the bottom of the package in the form of small bumps or balls. These balls are evenly distributed across the entire bottom surface of the package, allowing greater pitch between the individual terminals. The ball grid array configuration enables high-pin count devices to be manufactured less expensively with less delicate handling at installation. Our organic substrate-based packages employ a fine-pitch BGA design, which uses a plastic or tape laminate rather than a leadframe and places the electrical connections, or leads, on the bottom of the package rather than around the perimeter. The fine-pitch BGA format was developed to address the need for the smaller footprints required by advanced memory devices. Benefits of ball grid array assembly over leadframe-based assembly include: •smaller size; •smaller footprint on a printed circuit board; •better electrical signal integrity; and •easier attachment to a printed circuit board. The following diagram presents the basic component parts of a fine-pitch BGA package: 26 The following table presents the ball-count, description and end-user applications of organic substrate-based packages we currently assemble: Package Connections Description End-User Applications Mini BGA 24-400 Low-cost and space-saving assembly designed for low input/output count, suitable for semiconductors that require a smaller package size than standard BGA Memory, analog, flash memory, ASICs, radio frequency devices, personal digital assistants, cellular handsets, communication products, notebooks, wireless systems Fine-Pitch BGA 54-126 Our patented design for DRAM products that require high performance and chip scale package (CSP) Notebooks, cellular handsets, global positioning systems, personal digital assistants, wireless systems Very Thin Fine-Pitch BGA 24-200 Similar structure of Mini BGA package with thinner and finer ball pitch that is designed for use in a wide variety of applications requiring small size, high reliability and low unit cost Handheld devices, notebooks, disk drives, wireless and mobile communication products Land Grid Array (LGA) 11-204 Thinner and lighter assembly designed essential to standard BGA without solder balls, suitable for applications that require high electrical performance Disk drives, memory controllers, wireless, mobile communication products, game card, micro secure digital card Multi-Chip BGA 24-345 Designed for assembly of two or more memory chips (to increase memory density) or combinations of memory and logic chips in one BGA package Notebooks, digital cameras, personal digital assistants, global positioning systems, sub-notebooks, board processors, wireless systems Stacked-Chip BGA 24-349 Designed for assembly of two or more memory chips or logic and memory chips in one CSP, reducing the space required for memory chips Cellular handsets, digital cameras, personal digital assistants, wireless systems, notebooks, global positioning systems FC Chip-scale Package (FC CSP) 24-676 Better IC protection and solder joint reliability compared to direct chip attach (DCA) and chip on board (COB) Memory, logic, microprocessor, application processor (AP), baseband (BB), solid state device, radio frequency (RF) Multi-Chip Hybrid Package (FC+WB) 153-345 Designed for assembly of two or more memory chips or combinations of memory and logic chips in one BGA package with both of flip chip and wire bonding Universal Flash Storage (UFS), and BGA SSD Chip on Wafer (CoW) 5-30 Integrated two different functional chips to a closer form into a compact package. Low-cost solution compared to through-silicon via (TSV) Integrated MEMS Land Grid Array (LGA) for FPS(Finger Print Sensor) 20-52 Very thin clearance (50um) between chip & compound hard color coating with scratch resistance for protection and appearance matching of mobile devices Security protection for mobile devices, home, notebooks, etc. Wafer Level Chip Scale Package (WLCSP) 4-125 WLCSP package size is almost the same as die size. Simple assembly process flow, low cost. Small package suitable to apply on hand-held 3C electronic products Electronic Compass, audio converter, nor flash product, power control, sensor magnetometer, CMOS Image Sensor controller, Laser diode driver, power manager IC (PMIC) 27 Wafer Level CSP Wafer-level CSP (WLCSP) is the technology of packaging an integrated circuit at wafer level. WLCSP is essentially a true chip scale package (CSP) technology, since the resulting package is practically of the same size as the die. WLCSP has the ability to enable true integration of wafer fab, packaging, test, and burn-in at wafer level in order to streamline the manufacturing process undergone by a device start from silicon wafer to customer shipment. Most other kinds of packaging do wafer dicing first, and then puts the individual die in a plastic package and attaches the solder bumps. WLCSP involves the RDL, wafer solder bumping, while still in the wafer, and then wafer dicing. Benefits of WLCSP compare to general CSP package assembly include: •ultimate smaller package size; •smaller footprint on a printed circuit board; •very short circuit connection; and •cost effective packaging solution for small ICs. Package Connections Description End-User Applications WLCSP 4-219 Very small package size (identical to die size), suitable for the low pin count and require the small package size application Memory, ASICs, PMIC, MEMS devices, controllers, for mobile phones, tablets, ultra book computers and wearable products FC CSP 28 FC Chip Scale Package (FC CSP) construction utilizes the flip chip bumping (with solder bump or Cu pillar bump) interconnection technology to replace the standard wire-bond interconnect. It allows for a smaller form factor due to wire loop reduction and area array bumping. FC CSP includes the substrate or leadframe type solution making an attractive option for advanced CSP application when electrical performance is a critical factor. •Excellent electrical performance, very low interconnect parasitics and inductance compare to wirebond type. •High electrical current endurance (Cu pillar bump), ideal for high power and high speed logic solution. •High electrical performance (Cu pillar bump), ideal for lower return loss and higher insertion loss. •Reduce Bump Pitch and die size (Cu pillar bump vs. solder bump), ideal for increasing gross die/wafer. •Smaller package form factor by reducing the wire loop height and wire span compared to conventional wirebond package. Package Connections Description End-User Applications FC CSP 24-484 Superior electrical performance, smaller form factor Power devices, RF, High speed Logic devices, wireless, memory or portable applications Display Driver Semiconductors and Gold MCB Bumping We also offer assembly and testing services for display driver semiconductors. We employ COF and COG technologies for testing and assembling display driver semiconductors. In addition, we offer gold bumping and metal composite bump services to our customers. Note: Copper pillar service only for Max size: 9.9mmx9.4mm & pillar Account: 3,410 Chip-on-Film (COF) Technology COF technology provides several additional advantages. For example, COF is able to meet the size, weight and higher resolution requirements in electronic products, such as display panels. This is because of its structural design, including an adhesive-free two-layer tape that is highly flexible, bending strength and its capacity to receive finer patterning pitch. 29 COF package has been using for large-size and high-resolution panel display, especially on TFT-LCD and OLED TV set and NB as well. In recent years, there has been an observable trend with which the average inner lead pitch of COF package went down to 23um with more than 90% of market demand. High thermal dissipation packaging technology is available for mass production. And dual IC with high thermal dissipation COF packaging technology is ready for 8K TV market. 18um/16um inner lead pitch 2-metal layer COF package is ready for production of coming AR/VR gear requirement. And we can test display driver semiconductors with frequency up to 6.5Gbps to fulfill high speed data rate requirement. Minus temperature COF package testing technology is in production for automotive application requirement. The following diagram presents the basic components of 1-metal layer COF and 2-metal layer COF: The COF process involves the following steps: Chip Probing Screen out the defect chips which fail to meet the device spec. Wafer Lapping/Polish Laser Marking Laser Grooving Wafers are grounded or with polish to their required thickness. A laser mark is applied on IC backside in wafer form to provide product traceability. Application in wafer within Low-K material to reduce chipping of chips during dicing process. Die Saw Wafers are cut into individual dies, or chips, in preparation for inner lead bonding process. Inner Lead Bonding An inner lead bonding machine connects the chip to the printed circuit tape. Potting An underfill process to fill resin to protect the inner lead and chip. Potting Cure The potting cure process matures the resin used during the potting oven with high temperatures. Marking A laser marker is used to provide product identification. Final Testing To verify device spec. within electrical testing after assembly process. Taping To attach heat sink/spreader or stiffener material onto COF package. Inspection and Packing Each individual die with tape is visually or auto inspected for defects. The dies are packed within a reel into an aluminum bag after completion of the inspection process. Chip-on-Glass (COG) Technology COG technology is an electronic assembly technology that is used in assembling display driver semiconductors including TV/monitor, mobile and wearable products. Compared to the traditional bonding process for COF, the new COG technology requires lower bonding temperature. In addition, the COG technology reduces assembly cost as it does not use tapes for interconnection between the LCD, OLED panel and the printed circuit board. The major application of COG products is on TFT-LCD and AMOLED display of smart phone and automotive market, it integrates source, gate driver of display driver IC (DDIC) and touch or timing Controller IC into one chip, so the output channel is higher than COF products. For the market trend of thinner smartphone, 120um in IC thickness is released for mass production and much thinner IC thickness is in development. The COG assembly process involves the following steps: Chip Probing To screen out the defect chips which fail to meet the device spec. Wafer Lapping/Polish Wafers are ground or with polished to their required thickness. 30 Laser Marking A laser mark is applied on IC backside in wafer form to provide product traceability. Laser Grooving Application in wafer within Low-K material to reduce chipping of chips during dicing process. Die Saw Wafers are cut into individual dies, or chips, in preparation for the pick and place process. Auto Optical Inspection Process of wafer inspection is detecting defect to separate chips at pick and place station. Pick and Place Each individual die is picked and placed into a chip tray. Inspection and Packing Each individual die in a tray is visually or auto-inspected for defects. The dies are packed within a tray into an aluminum bag after completion of the inspection process. Bumping We also offer bumping services to our customers. Based on the major product portfolio (judged by internal metal composition), we provide: •Gold Family (Au bump, Au metal composite bump and Au RDL) Gold bumping technology, which is in high demand for LCD driver ICs. In 2023 and 2024, gold bumping development momentum will be emphasized on new products from OLED display penetration rate of smartphone, another focused business is that automotive category products continue to expand. In 2025, Display driver ICs business is challenged during geopolitical factor and major cost among of gold price is relative high cost and no sign to downward trend. We are well positioned to introduce our next-generation Silver-Alloy bump technology, which has successfully passed panel-level package reliability assurance (RA) verification. The objective is to complete mass-production qualification by the second quarter of 2026. The goal is to achieve performance and reliability comparable to gold bump solutions, enabling broader adoption in branded markets. •RDL technology As high speed, high performance and high accuracy requirement, many electronic devices need the capability of transferring higher current. By using Re-distribution layer (RDL) technology which can relocate to the PKG wire bonding position where necessary. ChipMOS can provide several electroplating metal thickness based on customer design request, including 2P1M, 2P2M and 3P2M structures. The min. Line/space of RDL could be 5/5um that makes integration of MCP and SIP achievable. To meet higher electrical performance requirements, we have developed and mass-production-qualified thicker RDL structures with total metal thickness up to 23.5 µm, which have been widely adopted in power and automotive applications in 2025. In parallel, our RDL platform has been expanded with flexible stack-up options, including 1M1P, 1P1M, and 1P2M, enabling optimized routing density, electrical performance, and cost efficiency across diversified product designs. We also continue to strengthen our capabilities in high-speed memory applications through close collaboration with leading customers, supporting increasingly stringent signal integrity and electrical performance requirements for next-generation memory devices. •Cu/Solder Family (WLCSP, Lead free solder plating and Cu Pillar) We believe that consumer electronics are driving the application growth of these processes. From small wearable gadgets, NOR flash in TWS (True Wireless Stereo) applications, power management devices to emerging AIoT/AI development are all included. We developed 12” WLCSP process for NOR flash to provide a thinner and smallest chip size for product trend. In 2025, Copper pillar and flip-chip assembly remain key packaging solutions for high-performance memory and power-related devices, with typical bump heights of 50–70 µm. Higher Copper pillar bump heights up to 100 µm are available for power management applications, while engineering development of fine-pitch micro bump technology with bump pitch down to 40 µm is ongoing for next-generation high-density interconnections. In addition, a new 12-inch WLCSP application for Mini LED TV driver ICs has been qualified and entered mass production in 2025, with stable shipment momentum. Overall, our WLCSP and Cu pillar process portfolio support diversified applications, including PMIC, wearable, storage, E-compass, CPS (smartphone), MCU, ALS, Mini LED TV drivers, and AI-related devices. Other Services Drop Shipment We offer drop shipment of semiconductors directly to end-users designated by our customers. We provide drop shipment services, including assembly in customer-approved and branded boxes, to a majority of our assembly and testing customers. Since drop shipment eliminates the additional step of inspection by the customer prior to shipment to end-users, quality of service is a key to successful drop shipment service. We believe that our ability to successfully execute our full range of services, including drop shipment services, is an important factor in maintaining existing customers as well as attracting new customers. 31 Software Conversion Program We work closely with our customers to provide sophisticated software engineering services, including test program conversion and related hardware design. Generally, testing requires customized testing software and related hardware to be developed for each particular product. Software is often initially provided by the customer and then converted by us at our facilities for use on one or more of our testing machines and contains varying functionality depending on the specified testing procedures. Once a conversion test program has been developed, we perform correlation and trial tests on the semiconductors. Customer feedback on the test results enables us to adjust the conversion test programs prior to actual testing. We also typically assist our customers in collecting and analyzing the test results and recommend engineering solutions to improve customers’ design and production processes. Customers We believe that the following factors have been, and will continue to be, important factors in attracting and retaining customers: •our advanced assembly and testing technologies; •our strong capabilities in testing and assembling DDIC/TDDI and other display panel driver semiconductors; •our focus on high-density memory products and logic/mixed-signal communications products; and •our reputation for high quality and reliable customer-focused services. The number of our customers as of February 29, 2024, February 28, 2025 and February 28, 2026, respectively, was 67, 68 and 70. Our top 15 customers in terms of revenue in 2025 were (in alphabetical order): Asahi Kasei Microdevices Corporation Chipone Technology (Beijing) Co., Ltd. Elite Semiconductor Microelectronics Technology Inc. GigaDevice Semiconductor (HK) Limited Himax Technologies, Inc. ILI Technology Corporation Integrated Circuit Solution Inc. Macronix International Co., Ltd. MediaTek Inc. Micron Technology, Inc. Nanya Technology Corporation Novatek Microelectronics Corp. Phison Electronics Corp. Raydium Semiconductor Corporation Winbond Electronics Corporation In 2023, our top three customers accounted for approximately 25%, 13% and 9% of our revenue, respectively. In 2024, our top three customers accounted for approximately 24%, 11% and 11% of our revenue, respectively. In 2025, our top three customers accounted for approximately 23%, 15% and 9% of our revenue, respectively. The majorities of our customers purchase our services through purchase orders and provide us three-month non-binding rolling forecasts on a monthly basis. The price for our services is typically agreed upon at the time when a purchase order is placed. The following table sets forth, for the periods indicated, the percentage breakdown of our revenue, categorized by geographic region based on the jurisdiction in which each customer is headquartered. Year ended December 31, 2023 2024 2025 Taiwan 81% 80% 87% Japan 6% 6% 5% PRC 8% 7% 6% Singapore 3% 4% 0% Others 2% 3% 2% Total 100% 100% 100% 32 Qualification and Correlation by Customers Our customers generally require that our facilities undergo a stringent “qualification” process during which the customer evaluates our operations, production processes and product reliability, including engineering, delivery control and testing capabilities. The qualification process typically takes up to eight weeks, or longer, depending on the requirements of the customer. For test qualification, after we have been qualified by a customer and before the customer delivers semiconductors to us for testing in volume, a process known as “correlation” is undertaken. During the correlation process, the customer provides us with test criteria; information regarding process flow and sample semiconductors to be tested and either provides us with the test program or requests that we develop a new or conversion program. In some cases, the customer also provides us with a data log of results of any testing of the semiconductor that the customer may have conducted previously. The correlation process typically takes up to two weeks, but can take longer depending on the requirements of the customer. Sales and Marketing We maintain sales and marketing offices in Taiwan, the United States and Mainland China. Our sales and marketing strategy is to focus on memory semiconductors in Taiwan, Japan, Singapore, Korea and the United States, logic/mixed-signal semiconductors in Taiwan, Japan and the United States, LCD, OLED, automotive panel and other display panel driver semiconductors in Japan, Korea, Taiwan, Hong Kong and Mainland China. As of February 28, 2026, our sales and marketing efforts were primarily carried out by teams of sales professionals, application engineers and technicians, totaling 30 staff members. Each of these teams focuses on specific customers and/or geographic regions. As part of our emphasis on customer service, these teams: •actively participate in the design process at the customers’ facilities; •resolve customer assembly and testing issues; and •promote timely and individualized resolutions to customers’ issues. We conduct marketing research through our in-house customer service personnel and through our relationships with our customers and suppliers to keep abreast of market trends and developments. Furthermore, we do product and system bench marking analysis to understand the application and assembly technology evolution, such as analysis on mobile handsets and Tablet, PC, wearable products. In addition, we regularly collect data from different segments of the semiconductor industry and, when possible, we work closely with our customers to design and develop assembly and testing services for new products. Sale will cooperate with internal technology expert to work closely with our customers as project kick off. We provide full turnkey service (from design-in stage/design for bumping and assembly/design for testing services) to achieve design for mass production for new products. These “co-development” or “sponsorship” projects can be critical when customers seek large-scale, early market entry with a significant new product. Research and Development To maintain our competitive edge for continued business growth, we continue our focus of our investment in new technology research and development. In 2023, 2024 and 2025, we spent approximately NT$1,093 million, or 5.1%, NT$1,163 million, or 5.1% and NT$1,077 million (US$34 million), or 4.5%, respectively, of our revenue on research and development. Our research and development efforts have been focused primarily on new technology instruction, improving efficiency and production yields of our testing, assembly and bumping services. From time to time, we jointly develop new technologies with local and international equipment and material manufacturing company to enhance the competitiveness. In testing area, our research and development efforts focused particularly on high speed probing, fine pitch probing capability and wafer level burn-in technology. Our projects include: •Ramped up high frequency testing capability of LCD, OLED, automotive panel and other display panel driver semiconductors; •Developing full temperature range (-40ºC~125ºC) of FT testing for automotive products; •Built up 12” fine pitch COF assembly capability for less than 18um inner lead pitch products; •Developing more flexible COF tape assembly for full-screen display application; •Developing “wafer level probing on copper pillar bump for 300mm wafers”; and •Developing centralized server test control system. In assembly and bumping areas, our research and development efforts were directed to: •Au height reduction, as part of cost reduction drive, 10um bump height COF package and 8um bump height COG package was released for production; •Wafer-level chip scale packaging and 3P2M Cu RDL processes; 33 •Fine-pitch Cu RDL process for WLCSP and RDL products; •Flip-chip CSP for DRAM and mixed-signal application; •3P/3M Cu pillar bumping for 300mm wafers high pin count products; •Fine pitch copper pillar process for micro bump structure; •Thicker Cu/Ni/Au RDL and 100im tall Cu pillar for PMIC application; •Developing fine pitch Cu RDL line width and space with 4um/4um for advanced re-distribution layer device design requirement; •Shrink ball size with ball mount technology and combine thinner wafer grind thickness to achieve thin WLCSP requirement; •Dual/Multi-chip assembly and module of flash products for SSD and eMMC applications; •Hybrid package by integration of wire binding & flip-chip process with passive components to offer total solution for UFS device; •DBG/SDBG implementation to enhance the capability of ultra-thin wafer lapping and dicing capabilities for stacked-die chip scale package; •Advanced thin core/core-free, flex substrate solutions for thin and flip chip packages; •2-metal layers COF assembly and COF SMT capabilities; •Qualified thermally enhanced COF and MCB COF and released for manufacturing; •Double-sided Heat Sink/ High conductivity material development is applied in thermal packaging services for high-resolution panels; •Source & Gate ICs integrated technology development is used in product applications with narrow border panels; •Develop new 2P2M RDL structure to use pure Cu RDL for fine pitch complex circuit and Improved Cu RDL undercut instead of Cu-Ni-Au composite structure; •Develop Ultra Fine Pitch (UFP) COF assembly and testing technology; •Implement new thermal conductive resin with higher conductivity for COF package; •Enhance Pb free ball level capability (temperature cycle > 1000 cycles); and •High Frequency & Low loss Product Substrate design for FCCSP. •Develop 2P2M with thick Cu RDL and taller Cu Pillar bump height technology for power management chip product. •Develop 12 inch stand-alone thinner technology for WLCSP. •Develop extremely narrow IC width (<0.42mm) of display driver COF packaging technology services. •Technical services for COF packaging and applying for non-display product. •DDR5 DRAM assembly technology development. •Thermal enhanced Flip-chip BGA with Heat sink assembly technology development. 34 For new product and product enhancement work in 2017, our work concentrates on three key development programs: 3D WLCSP, biometric sensor package solutions, and flip chip technology. In the bumping area, we completed customer qualification of 300mm wafer Au bumping process in 2012 and started volume production in the fourth quarter of 2012. Development of Cu plating enables the entry of WLCSP, RDL and flip chip market and Cu RDL applied on DRAM wafer for SiP product is qualified in 2016. Turnkey services of WLCSP and flip chip QFN have been implemented for mass production in 2013 based on the successful technology developments. In 2012, we also initiated both 200mm and 300mm Cu pillar bumping engineering work and, related packaging technologies are being developed for mixed-signal and memory products in 2013. It is also qualified on power management IC product in 2016. According wearable device trend, we miniature fine-pitch Cu RDL process for WLCSP and RDL products, we shrink ball size with ball mount technology and combine thinner wafer grinded thickness to achieve thin WLCSP structure in 2020 which used in Auto Focus, OIS (Optical Image Stabilization) system and Hall motor sensor. By integrating WLCSP bumping, copper pillar bumping and flip chip assembly capability, an integrated WLCSP (CoW or 3D WLCSP) is developing in 2015, and qualified the structure and process verification in 2016. We adopt FC Chip Scale Package to implement in USB4/DP2.0 Re-Driver, PCIe 5.0 Re-Driver Product in 2021. Meanwhile, fingerprint sensor (FPS) packaging solution by LGA was also developed for smartphone demand in 2015. More and more integrated function of DDIC, TDDI and FPS, is requested for smartphone application, therefore 2-metal layers COF solution and COF SMT are developed to provide the package solution since 2019. Moreover, the improved OLED panel yield rate has also increased its adoption in smartphones, leading to diverse applications such as in-display fingerprint sensors. Since 2013, in-process engineering advancement allowed us to extend our wirebond technology to service MEMS products. To further achieve cost reduction, alloy wire and 0.6 mil Au wirebond processes were also developed. In 2018, we continued to work on the expansion of multi-chip NAND packages offerings, and 12” fine pitch COF assembly capability. Capability of handling miniature molded packages has been extended to 1x1 mm size and various improvements will also be made in production equipment to enhance throughput and efficiency. In 2019, we launched SDBG technology to implement multi-chip assembly and module of flash products for NAND Flash applications for SSD and eMMC applications. As of February 28, 2026 we employed 651 employees in our research and development activities. In addition, other management and operational personnel are also involved in research and development activities but are not separately identified as research and development professionals. We maintain laboratory facilities capable for materials and electrical characterizations to support production and new product development. Computer simulation is used to validate both mechanical and electrical models in comparison to measurement results. Enhancement of Shadow Moiré and Micro Moiré equipment was carried out to support MCP and flip chip package warpage and residue stress characterization. We also setup up mold flow simulation capability to predict assembly risk. In Advanced Packaging Lab, rheology measurement capability and high frequency electric simulation capability were established, aimed at expanding capability for material selection and inspection to support flip chip introduction and various resin characterizations. For customer application request, we enhance our thermal simulation capability in 2022. An analytical laboratory has been built out in our bumping line providing timely support to manufacturing operations. Quality Control We believe that our reputation for high quality and reliable services have been an important factor in attracting and retaining leading international semiconductor companies as customers for our assembly and testing services. We are committed to delivering semiconductors that meet or exceed our customers’ specifications on time and at a competitive cost. We maintain quality control staff at each of our facilities. Our quality control staff typically includes engineers, technicians and other employees who monitor assembly and test processes in order to ensure high quality. We employ quality control procedures in the following critical areas: •sales quality assurance: following market trends to anticipate customers’ future needs; •design quality assurance: when developing new testing and assembly processes; •supplier quality assurance: consulting with our long-term suppliers; •manufacturing quality assurance: through a comprehensive monitoring program during mass production; and •service quality assurance: quickly and effectively responding to customers’ claims after completion of sale. All of our facilities have obtained ISO 26262 road vehicles-functional safety system certification in December 2019 and obtained IATF 16949 quality system certification in December 2017. In addition, our facilities in Hsinchu and Tainan have been recertified with ISO 9001 for substantial revision since 2015. 35 IATF 16949 certification system seeks to integrate quality management standards into the operation of a company and emphasizes the supervision and measurement of process and performance. An ISO 9001 certification is required by many countries for sales of industrial products. In addition to the quality management system, we also earned the 1998 QC Group Award from The Chinese Society of Quality, which is equivalent to the similar award from the American Society of Quality and certified ISO17025 in 2000. In 2003, ChipMOS passed SONY Green Partner (Tier 2) certification through its ProMOS channel, and in 2009, ChipMOS obtained SONY Green Partner (Tier 1) certification due to its direct business relationship with SONY. The Sony certificates will continue to be maintained uninterrupted until now. Our laboratories have also been awarded Chinese National Laboratory accreditation under the categories of reliability test, electricity and temperature calibration. Our assembly and testing operations are carried out in clean rooms where air purity, temperature and humidity are controlled. To ensure the stability and integrity of our operations, we maintain clean rooms at our facilities that meet U.S. federal 209E class 100, 1,000, 10,000 and 100,000 standards. A class 1,000 clean room means a room containing less than 1,000 particles of contaminants per cubic foot. We have established manufacturing quality control systems which are designed to maintain reliability and high production yields at our facilities. We employ the most advanced equipment for manufacturing quality and reliability control, including: •Temperature cycling tester (TCT), thermal shock tester (TST) and pressure cook tester (PCT), and highly accelerated temperature/humidity stress tester (HAST) for reliability analyses; •Scanning acoustic tomography (SAT) and scanning electronic microscope (SEM) for physical failure analysis; •Semi-Auto prober, curve tracer and DC tester station for electrical failure analysis; •Atomic absorption spectrometer (AA), inductively coupled plasma optical emission spectrometer (ICP-OES) and automatic potentiometric titrator (AP), UV-Visible Spectrophotometer (UV-VIS), Cyclic Voltammetric Stripping (CVS) and Ultra Performance Liquid Chromatography (UPLC) for chemical analysis In addition, to enhance our performance and our research and development capabilities, we also installed a series of high-cost equipment, such as temperature humidity bias testers, low temperature storage-life testers and highly accelerated stress testers. We believe that many of our competitors do not own this equipment. As a result of our ongoing focus on quality, in 2025, we achieved monthly assembly yields of an average of 99.92% for our memory and logic/mixed-signal assembly packages, 99.99% for our COF packages, 99.97% for our COG packages and 99.96% for our bumping products (including gold bump, RDL and WLCSP). The assembly yield, which is the industry standard for measuring production yield, is equal to the number of integrated circuit packages that are shipped back to customers divided by the number of individual integrated circuits that are attached to lead frames or organic substrate. Raw Materials Semiconductor testing requires minimal raw materials. Substantially all of the raw materials used in our memory and logic/mixed-signal semiconductor assembly processes are interconnect materials such as leadframes, organic substrates, gold wire and molding compound. Raw materials used in the LCD, OLED, automotive panel and other display panel driver semiconductor assembly and testing process include gold, carrier tape, resin, spacer tape, plastic reel, aluminum bags, and inner and outer boxes. Cost of raw materials represented 19%, 20% and 25% of our revenue in 2023, 2024 and 2025, respectively. We do not maintain large inventories of leadframes, organic substrates, gold wire or molding compound, but generally maintain sufficient stock of each principal raw material for approximately two to three month’s production based on blanket orders and rolling forecasts of near-term requirements received from customers. Shortages in the supply of materials experienced by the semiconductor industry have in the past resulted in price adjustments. See “Item 3. Key Information—Risk Factors—Risks Relating to Our Business—If we are unable to obtain raw materials and other necessary inputs from our suppliers in a timely and cost-effective manner, our production schedules would be delayed and we may lose customers and growth opportunities and become less profitable” for a discussion of the risks associated with our raw materials purchasing methods. For example, with the exception of aluminum bags and inner and outer boxes, which we acquire from local sources, the raw materials used in our COF process and for modules are obtained from a limited number of Japanese suppliers. 36 Competition The independent assembly and testing markets are very competitive. Our competitors include large IDMs with in-house testing and assembly capabilities and other independent semiconductor assembly and testing companies, especially those offering vertically integrated assembly and testing services, such as Advanced Semiconductor Engineering Inc., Amkor Technology, Inc., Chipbond Technology Corporation, King Yuan Electronics Co., Ltd., Powertech Technology Inc., Jiangsu Changjiang Electronics Technology Co., Ltd. and United Test and Assembly Center Ltd. We believe that the principal measures of competitiveness in the independent semiconductor testing industry are: •engineering capability of software development; •quality of service; •flexibility; •capacity; •production cycle time; and •price. In assembly services, we compete primarily on the basis of: •production yield; •production cycle time; •process technology, including our COF technology for LCD, OLED, automotive panel and other display panel driver semiconductor assembly services; •quality of service; •capacity; •location; and •price. IDMs that use our services continually evaluate our performance against their own in-house assembly and testing capabilities. These IDMs may have access to more advanced technologies and greater financial and other resources than we do. We believe, however, that we can offer greater efficiency and lower costs while maintaining an equivalent or higher level of quality for three reasons: •firstly, we offer a broader and more complex range of services as compared to the IDMs, which tend to focus their resources on improving their front-end operations; •secondly, we generally have lower unit costs because of our higher utilization rates and thus enabling us to operate at a more cost-effective structure compared to the IDMs; and •finally, we offer a wider range of services in terms of complexity and technology. Intellectual Property As of February 28, 2026, we held 273 patents in Taiwan, 76 patents in the United States, 149 patents in Mainland China, 1 patent in the United Kingdom and 2 patents in Korea and Japan, respectively, relating to various semiconductor assembly and testing technologies. These patents will expire at various dates through to 2044. As of February 28, 2026, we also had a total of 11 pending patent applications in Taiwan, and 68 in Mainland China. In addition, we have registered “ChipMOS” and its logo as trademarks in Taiwan, the United States, Mainland China, Singapore, Hong Kong, Korea, Japan, the United Kingdom and the European Community. We expect to continue to file patent applications where appropriate to protect our proprietary technologies. We may need to enforce our patents or other intellectual property rights or to defend ourselves against claimed infringement of the rights of others through litigation, which could result in substantial costs and a diversion of our resources. See “Item 3. Key Information—Risk Factors—Risks Relating to Our Business—Disputes over intellectual property rights could be costly, deprive us of technologies necessary for us to stay competitive, render us unable to provide some of our services and reduce our opportunities to generate revenue”. 37 Government Regulations As discussed above under “—Intellectual Property”, governmental regulation of our intellectual property may materially affect our business. The failure to protect our property rights would deprive us of our ability to stay competitive in the semiconductor industry. Our intellectual property rights are protected by the relevant patent and intellectual property agencies of the European Community, the United Kingdom, the United States, Mainland China, Korea, Japan and Taiwan. Environmental and Climate Change Matters Semiconductor testing does not generate significant pollutants. The semiconductor assembly and gold bumping process generate stationary acid, alkali and VOC pollutions, principally at the plating and etching stages. Water waste is produced when silicon wafers are ground thinner, diced into chips with the aid of diamond saws and cleaned with running water. In addition, excess materials, either on leadframes or molding process, are removed from assembled semiconductors in the trimming and de-junking processes, respectively. We have various treatment equipment for wastewater and air pollutants at our assembly and bumping facilities. Since 2001, we have adopted certain environmental friendly production management systems, and have implemented certain measures intended to bring our all processes in compliance with the Restriction of Hazardous Substances Directive/EC issued by the European Union and our customers. We believe that we have adequate and effective environmental protection measures that are consistent with semiconductor industry practices in Taiwan. In addition, we believe we are in compliance in all material respects with current environmental laws and regulations applicable to our operations and facilities. All of our facilities in Taiwan have been certified as meeting the ISO 14001 environmental standards of the International Organization for Standardization, and all of our facilities in Taiwan have been certified as meeting the ISO 45001 standards of the International Organization for Standardization. Our facilities at Hsinchu Science Park, Chupei, Hukou, Hsinchu Industrial Park and Southern Taiwan Science Park have won numerous awards including “Green Factory Label” from 2013 to 2025, “Enterprises Environmental Protection Gold Grade Award” in 2018 and 2019, “Occupational Safety and Health Excellent Award” in 2016, 2017, 2021 to 2025, “Green Building Label” in 2014 and 2017 up to now. We are also certified the “Health Promotion Awards” from 2012 to 2025. We continue to encourage our employees to participate in community environmental campaigns and better environmental friendly practices. We will continue to enhance related management to reduce industrial waste, save energy and control pollution. For products in conformity with Green Product Requirement, the Company obtained Green Partner certification from Sony Corporation of Japan. Furthermore, we passed QC 080000 certification and “Greenhouse Gas Verification Statement” (“ISO 14064-1”) from 2013 until now. We further confirmed many products’ CFP “Carbon Footprint Verification Statement” (“ISO 14067”) and WFN “Water Footprint Verification Statement” (“ISO 14046”). At the same time, Tainan, Hsinchu, Chupei and Hukou plants passed the certification of energy management system (“ISO 50001”) in 2014, 2017 and 2025 up to now. For materials management, we passed the “Material Flow Cost Accounting (MFCA, ISO 14051)” to reduce the loss. Our policy is to pay attention to the environment issues by standardizing on green, environmental friendly products, cleaner process and enhance supplier chain management to meet ChipMOS’ Corporate Social Responsibilities. As an enterprise, ChipMOS understands the importance of carrying out environmental protection in action. By referencing the Task Force on Climate-related Financial Disclosures (“TCFD”) framework developed by the Financial Stability Board (“FSB”) and began in 2021, we have identified the management needed over risks and opportunities associated with climate change, and further attained a comprehensive overview on the effects of climate change. Besides depleting the Earth of her resources, energy consumption also generates carbon dioxide, leading to greenhouse effects. Hence, effective energy use will help to mitigate impacts on the environment. Due to the nature of the technology industry, ChipMOS is classified as one of the major electricity consumers per regulations from the Energy Administration, MOEA. Upholding our principle of treasuring energy consumption, we began to systematically initiate energy conservation actions in 2012. We continue to introduce various energy efficient technologies and facilities, and on top of Tainan fab’s voluntary introduction of ISO 50001 Energy Management System in 2014, Hsinchu fab, Chupei and Hukou plants also achieved the ISO 50001 Energy Management System certification in 2017 and 2025. We actively promoted the use of renewable energy sources in 2020 and built solar power generation facilities to continuously increase the consumption ratio of renewable energies. Environmental, Social and Governance (“ESG”) Initiatives and Sustainable Development Goals (“SDGs”) Linkings ChipMOS adheres to the mission of “Acting with Integrity, Strengthening Environmental Protection, and Care for the Disadvantaged” and has formulated the “Sustainable Development Principles” and “Corporate Sustainability Policy”, which are adopted by the Board of Directors as the highest principle for the Company to promote sustainable development. 38 ChipMOS ESG Committee is the highest decision-making sustainability management organization within the Company. The Chairman & President acted as the Chairperson and be the top of management executives of ESG Committee, the Executive Vice Presidents holds the highest management position for the south and north fabs; the key members are senior executives of each business unit, who work together to set sustainable development goals in line with the Company’s business strategy and implement sustainability plans in daily operations. The ESG Committee reports quarterly to the Board of Directors on the status and results of sustainability projects, including issues such as promotion of net-zero emission for sustainability (including GHG inventories and verification), annual sustainability results (including stakeholder communication), mid- and long-term ESG goals, and results of risk management. ChipMOS formulates sustainability vision by integrating sustainability policy, organizational vision, and core missions, and inspects the vision’s link to the United Nations’ SDGs. In accordance with the Company’s ESG development direction and ChipMOS Material Topics, ChipMOS focuses on 10 major SDGs (SDG 3, SDG 4, SDG 6, SDG 7, SDG 8, SDG 11, SDG 12, SDG 13, SDG 16, SDG 17) to respond and set measurable and timely internal management objectives. We have launched sustainable actions for all aspects during our business management, including: continuing to enhance corporate governance, complying with ethical management and being committed to the R&D and innovation of core technologies to realize our commitment and responsibilities to employees; and actively invest in green production to reduce harmful effects on the environment during production processes and continuing to enhance resource utilization efficiency to protect the environment. Internally, we persist in the protection and care for employees’ health and welfare while striving in employee development and assisting in their career development. Externally, we are deeply engaged in environmental sustainability and social welfare. Green Production and Green Manufacturing Global warming and climate change have become phenomenon that enterprises around the world need to address. ChipMOS continues to follow the Paris Agreement and strives to increase the use of renewable energy and improve the efficiency of energy use on the basis of strengthening adaptation to climate change, so as to reducing greenhouse gases and controlling global temperature rise, on top of enhancing adaptability to climate change. ChipMOS is committed to building solar power generation system up to 10% of the contracted power generation in 2025, planning various energy saving goals and achieve a company-wide energy saving rate more than 1%, and implementing products’ Carbon and Water Footprint and Material Flow Cost Accounting and more. Through reducing consumption and carbon emissions, we hope to reduce the impacts on the environment. At the same time, we also continue to educate employees to enhance their awareness of environmental protection. These efforts have also been extended to our suppliers and stakeholders as we hope to work collectively to become a low-carbon, energy-saving, and green enterprise. Employee Value and Talent Developing We are committed to equality and strive to provide equal employment opportunities. We protect the rights of our workers and respect every employee, and we have created a positive and friendly workplace environment. ChipMOS has set up comprehensive talent development framework and system and invested sufficient resources toward the training for Leadership, Technology, General Management, Quality, and for Newcomer Orientation. At the same time, talent development strategies have also been formulated to achieve talent development goals. Long-Term Customer Partnerships ChipMOS promises that products and services delivered to customers can meet their needs, are competitive, and are served on a timely basis. Upholding the principle of customer service, we provide comprehensive products and services from a customer oriented perspective with the aim of becoming customers’ trusted, long-term partners. Social Inclusion and Local Community Partnership With the two major visions, namely “Environmental Sustainability” and “Public Welfare Practice”, ChipMOS has developed four major development aspects, including “Environment-Friendly”, “Community Feedback”, “Care for the disadvantaged” and “Talent Cultivation”, linking the 17 UN SDGs, while focusing on three SDGs (SDG 3, SDG 4 and SDG 11). Environmental Sustainability Various plans are conducted based on the two major aspects, “environmental friendliness” and “community feedback”. For the implementation strategy, we start from the Company internally and work with the community. Other than taking care of the surrounding environment, we also work together with our employees to love the Earth with diverse approaches. It is expected to take practical actions for fighting against climate change and global warming together. 39 Fulfillment of public welfare ChipMOS insists to the philosophy of “taking from the society and using it for the society”, by connecting various internal and external resources, the prioritized focus are “cares for the disadvantaged” and “cultivation of young talents” for the public welfare practice, with active collaborations with local communities, schools and social welfare organizations. It is hoped to exert the full forces as a corporate, and invite ChipMOS employees to jointly support the public welfare activities, and extend the influence of public welfare to all corners of Taiwanese society through more diverse methods, for achieving common prosperity of the society, and implementing the spirit of corporate social citizen. Corporate Governance ChipMOS follows the “Articles of Incorporation” and “Corporate Governance Best Practice Principles” and relevant laws and regulations, formulates the Corporate Governance structure, establishes a good Corporate Governance system, abides by laws and regulations, and operates in good faith to ensure the steady operation and growth of the Company. ChipMOS strengthens the supervision and management of the Company’s operation through the Board of Directors, strives to protect the rights and interests of shareholders and other stakeholders, actively communicates and interacts with stakeholders, continuously improves information transparency and implements sustainable corporate development, which are the main priorities for development promoted by Corporate Governance. ChipMOS continues strengthening Corporate Governance management, including safeguarding shareholders’ rights and interests, enhancing the operation of the Board of Directors, strengthening internal control Risk management, improving information transparency, and implementing sustainable development, so as to actively improve the level of Corporate Governance and allow stakeholders to understand the effectiveness of the implementation of various policies. For further information on our ESG initiatives and SDGs linking, please see our annual Sustainability Reports, which are available on our website at https://www.chipmos.com/english/csr/report.aspx. The information contained on our website is not incorporated herein by reference and does not constitute part of this annual report. Insurance We maintain insurance policies on our buildings, equipment and inventories. These insurance policies cover property damages due to all risks, including but not limited to, fire, lightning and earthquakes. The maximum coverage of property insurance for the Company is approximately NT$133.35 billion. Insurance coverage on facilities under construction is maintained by us and our contractors, who are obligated to procure necessary insurance policies and bear the relevant expenses of which we are the beneficiary. We also maintain insurance on the wafers delivered to us while these wafers are in our possession and during transportation from suppliers to us and from us to our customers. Employees See “Item 6. Directors, Senior Management and Employees—Employees” for certain information relating to our employees. Taxation See “Item 5. Operating and Financial Review and Prospects—Taxation” for certain information regarding the effect of ROC tax regulations on our operations. Facilities We provide testing services through our facilities in Taiwan at following locations: Chupei, the Hsinchu Industrial Park, the Hsinchu Science Park, and the Southern Taiwan Science Park. We provide assembly services through our facility at the Southern Taiwan Science Park. We own the land for our Hsinchu Industrial Park testing facility and Chupei facility and we lease two parcels of land for our Hsinchu Science Park testing facility with lease expiration in year 2027 and 2034, respectively, and two parcels of land for our Southern Taiwan Science Park facility with lease expiration in year 2032 and 2044. 40 The following table shows the location, primary use and size of each of our facilities, and the principal equipment installed at each facility, as of February 28, 2026. Location of Facility Primary Use Floor Area (m2) Principal Equipment Chupei, Hsinchu Testing/Gold Bumping 40,526 10 steppers 17 sputters 336 testers Hsinchu Industrial Park Testing 25,864 165 testers 18 burn-in ovens Hsinchu Science Park Testing 31,169 201 testers 53 burn-in ovens Southern Taiwan Science Park Assembly/Testing 184,325 955 wire bonders 105 inner-lead bonders 731 testers Equipment Testing of Memory and Logic/Mixed-Signal Semiconductors Test equipment is the most capital-intensive component of the memory and logic/mixed-signal semiconductors test business. Upon the acquisition of new test equipment, we install, configure, calibrate and perform burn-in diagnostic tests on the equipment. We also establish parameters for the test equipment based on anticipated requirements of existing and potential customers and considerations relating to market trends. As of February 28, 2026, we operated 702 testers for testing memory and logic/mixed-signal semiconductors. We generally seek to purchase testers with similar functionality that are able to test a variety of different semiconductors. We purchase testers from international manufacturers Advantest Corporation. In general, particular semiconductors can be tested using a limited number of specially designed testers. As part of the qualification process, customers will specify the machines on which their semiconductors may be tested. We often develop test program conversion tools that enable us to test semiconductors on multiple equipment platforms. This portability among testers enables us to allocate semiconductor testing across our available testing capacity and thereby improve capacity utilization rates. If a customer requires the testing of a semiconductor that is not yet fully developed, the customer consigns its testing software programs to us to test specific functions. If a customer specifies test equipment that is not widely applicable to other semiconductors we test, we require the customer to furnish the equipment on a consignment basis. We will continue to acquire additional test equipment in the future to the extent market conditions, cash generated from operations, the availability of financing and other factors make it desirable to do so. Some of the equipment and related spare parts that we require have been in short supply in recent years. Moreover, the equipment is only available from a limited number of vendors or is manufactured in relatively limited quantities and may have lead time from order to delivery in excess of six months. Assembly of Memory and Logic/Mixed-Signal Semiconductors The number of wire bonders at a given facility is commonly used as a measure of the assembly capacity of the facility. Typically, wire bonders may be used, with minor modifications, for the assembly of different products. We purchase wire bonders principally from Shinkawa Co., Ltd. and Kulicke & Soffa Industries Inc. As of February 28, 2026, we operated 955 wire bonders. In addition to wire bonders, we maintain a variety of other types of assembly equipment, such as wafer grinders, wafer mounters, wafer saws, stealth dicing, die separator, die bonders, automated molding machines, laser markers, solder platers, pad printers, dejunkers, trimmers, formers, substrate saws and lead scanners. Gold Bumping, Assembly and Testing of LCD, OLED, automotive panel and Other Display Panel Driver Semiconductors We acquired TCP-related equipment from Sharp to begin our TCP-related services. We subsequently purchased additional TCP-related testers from Advantest Corporation and assembly equipment from Shibaura Mechatronics Corp. As of February 28, 2026, we operated 10 steppers and 17 sputters for gold bumping, 105 inner-lead bonders for assembly and 731 testers for LCD, OLED, automotive panel and other display panel driver semiconductors. We are currently in the process of purchasing additional test equipment. The test equipment can be used for the COF and COG processes, while the inner-lead bonders are only used in the COF processes. The same types of wafer grinding, auto wafer mount and die saw equipment is used for the COF and COG processes. In addition, auto inspection machines and manual work are used in the COG process, which is more labor-intensive than the COF processes. 41